Problem Statement: http://www.cs.utexas.edu/users/hds/cs352/assignments/sep24/sep24.pdf
Sample Solution: http://docs.google.com/Doc?id=dgt9wvxh_54c7ggxk
Points Distribution(Question:Points)--> 1:10 2:20 3:20
1. a) jr rs
Jump register is implemented as PC = R[rs]
rs is Instruction[25-21] in Fig 5.17 which is used to select a register. Data is read from Read data 1 which is R[rs]. To assign this value to PC we add a multiplexer between output of Read data 1 and input of PC.
Extra Controls
A new control for the new multiplexer is added in the control unit. When jr is asserted, this control is asserted as well. We do not care about other signals.
b) lui rt, imm
Load upper immediate is implemented as
R[rt] := (imm << 16); PC = PC + 4;
Immediate (Instruction[15-0]) is left shifted by 16 and is channeled to input of Write data of register file. A new control for a new multiplexer is added in control unit.
Extra Controls
The new control is 1.
rt is Instruction[20-16] so RegDst is 0.
Since lui writes to register, RegWrite is 1.
branch is 0, since we want to increment PC
MemRead and MemWrite are 0, since we don't read or write memory.
We don't care about ALU and other controls.
2)
Assume that we have a multi-cycle MIPS processor as described in figure 5.28.
Give a complete description of how the following instructions (your description must
give the settings of all of the control signals and the contents of each of the effected
registers for each cycle:
a. sub $t3, $t1, $t2 equivalently sub $11, $9, $10
b. lw $s0, 4($t4) equivalently lw $16, 0x0004($12)
Assume that the following registers contain:
$t1 = 0x00000010, $t2 = 0x00000002, $t3 = 0x00000000, $t4 = 0x10001000
mem[0x10001000] = 0xfffffffd,
mem[0x10001004] = 0x00000789,
mem[0x10001008] = 0x00001111
Ans)
The control signals are as in Fig 5.38 with a correction in state 4: RegDst = 0, MemtoReg=1. The effect on registers are following:
a) sub $t3, $t1, $t2 equivalently sub $11, $9, $10
(1) Instruction Fetch
IR <= Memory[PC]
PC <= PC + 4
IR = 0x014B4822
(2) Instruction Decode and Register Fetch
A <= Reg[IR[25:21]]; (A:=R[rs])
B <= Reg[IR[20:16]]; (B:=R[rt])
A = 0x00000010, B = 0x00000002
(3) Execution
ALUOut <= A op B; (ALUOut=A-B)
ALUOut = 0x0000000E
(4) R-type Instruction Completion
Reg[IR[15:11]] <= ALUOut; (R[rd]=ALUOut)
$t3 = 0x0000000E
b) lw $s0, 4($t4) equivalently lw $16, 0x0004($12)
(1) Instruction Fetch
IR <= Memory[PC]
PC <= PC + 4
IR = 0x8D900004
(2) Instruction Decode and Register Fetch
A <= Reg[IR[25:21]]; (A:=R[rs])
A = 0x10001000
(3) Memory Address Computation
ALUOut <= A + sign-extend (IR[15-0]);
ALUOut = 0x10001004
(4) Memory Access
MDR <= Memory [ALUOut];
MDR = 0x00000789
(5) Memory Read Completion
Reg[IR[20:16]] <= MDR;
$s0 = 0x00000789
3.
http://spreadsheets.google.com/pub?key=p
| a.CPI = | 4.19 | c.New CPI = | 4.56 | ||
| Instruction count = | time * clocks per sec / clocks per Instr | ||||
| b. | 63007159905 | ||||
| c.New CPI = | 4.56 | ||||
| Execution Time = | Instr.Count * clocks per Instr./clocks per sec | ||||
| d. | 95.77088305 | ||||
